Chapter 8 : Nanoelectronics
The technology that deals with the design, construction and applications of electronic circuits and devices whose overall dimensions or building blocks are on a nanometer scale.
Possible electronic devices in computers that can be scaled down to Nano levels:
Nano-electronics may be implemented by two basic approaches:
Topics covered in this snack-sized chapter:
Creating small geometries by lithography.
Creating small geometries by utilizing the properties of the materials.
MOSFET: “Metal-Oxide-Semiconductor Field-Effect Transistor”.
At present, the MOSFET is the dominant device in GSI circuits because it can be scaled to smaller dimensions than other types of devices.
The dominant technology for MOSFET is CMOS in which both N-channel and P-channel devices are provided on the same chip.
CMOS technology has the lowest power consumption of all IC technology.
In 1970s, gate length was and device area was approximately
In present MOSFETs, the gate length is less than .
Start with p-type, lightly doped , oriented silicon.
Form oxide isolation region.
Define active area with photoresist mask and a boron chanstop layer implanted through nitride-oxide layer.
Grow gate oxide and adjust threshold voltage by implanting boron ions (enhancement mode device).
Form gate by depositing doped polysilicon. Pattern gate in source and drain region.
Implant arsenic to form source and drain.
P-glass is deposited and flowed.
Contact windows defined and etched in P-glass. is deposited and patterned.
Top view of completed MOSFET